Design of the system
To memorize a dynamic changing process of one signal or serial signals(Fig.1), we have proposed an idea of constructing a unique memory device with sequential memory structure, called MemOrderY, to record one changing signal in multiple time periods. Besides the signal we want to record, the Target signal, a Clock signal with the manner of oscillation is brought into the system to provide the circuit with the information about time. And we have chosen serine integrases to build the main parts due to their diversity, orthogonality between each other and high efficiency. Here, we are going to illustrate how we design the simplest version of this memory device, the two-signal system, which records one changing signal in two time periods.
Overview of the whole circuit
As you can find in Fig.2, the whole circuit of two-signal system is made up of three parts: logic gates, sequential memory structures and basic orthogonal memory modules. Logic gates are where the signals from Target and Clock signals are processed. And sequential memory structures control the whole memory schedule, being the core part of this project. Integrases labeled with numbers belong to this part while those labeled with English letters belong to next part, basic orthogonal memory modules. IntA and IntB are true executors of signal memorizing, and designed to record the signal in early and late time period respectively.
The input of logic gates are Target and Clock signals(Fig.3 a). It is obvious that Target signal is the one we want to record. Although Clock signal seems unrelated, it is helpful to provide the circuit with time information. It serves as a time license. When Clock signal is on for the first time, the following parts start to work and record the present information of Target signal. After that, Clock signal turns off, stopping recording and beginning to prepare for the second record in the next time period.
Logic gates(Fig.3 b) are employed in this project to process the raw signal from Target and Clock, and control three promoters, PC, P-C and PC&T. As a result, this part is like a bridge between the signals and sequential memory structures, which makes both signals can be highly customized to record various targets of interest with appropriate clocks.
Sequential memory structures
The key step in recording the changing process of a signal is the distinguishing between the signals recorded at different time point. We accomplished the distinguishing work with our sequential memory structure. The structure is consists of segments of orthogonal memory modules, each one is capable of responding to the target signal and executing the memory process alone. The structure is under the strict control of the clock signal and logic gates mentioned above, so that only one memory module is activated during one recording period. The structure is delicately designed in a way that different memory modules are turned on and off in a sequential order corresponding to their spatial relations on the plasmid. By answering to the same signal at different time point with different memory modules, the circuit can distinguish these signals and finally put them in the proper sequential order. The structure is the most important part of our sequential memory device. And it is the only difference between Two-signal system and Multi-signal system.
The main idea of this part is to make the memory modules follow the order from the Clock signal. Here we made an interactive animation below to help you to better understand these important structures.
This animation will show you how our system works when it meets the Target Signal below.
Basic orthogonal memory modules
This part is a combination of existing memory devices. In one time period, only one of these orthogonal devices in this part are ready to work. And each device only correspond to this time period, and respond to the inducer in this time period. We choose integrases to build this part. In the above animation, except Time 1 and Time 3 which serve as recording interval, Time 2 and Time 4 are corresponding to IntA and IntB respectively. Of course, any orthogonal memory devices can be used here with similar design.
The orthogonality of the integrases
We have to ensure the orthogonality of our integrases because it is required for building sequential memory structures and basic orthogonal memory modules. Five serine integrases were obtained from the start of our project. They are phiBT1, Bxb1, phiC31, phiRv1 and TG1. We designed and conducted the experiment based on PCR, which implied good orthogonality between each of them, except for the crosstalk between phiRv1 and attB/P sites of phiC31.
Two plasmids are adopted in this test. Before conducting our experiment, we made competent TOP10 expressing transcriptional factors, which had already transformed with pUC19-LacI-AraC high copy plasmid(Fig.4 a). On the testing plasmid, all five attB and attP pairs are aligned together(Fig.4 b). Some notices of this alignment are listed here: 1. attB/P of one integrase are in opposite direction; 2. There is no nucleotide between former attP and latter attB; 3. Primer pairs(Fig.4 c) are designed to determine by PCR whether each attB/P has been inverted by the integrase. One of the five integrases is also expressed using PBAD controlled by L-arabinose. We tested each sites by PCR after inducing or not inducing with 0.27%(w/v) L-arabinose for 16 hours.
As shown in Fig.5, bands on lane A and B indicate the existence of original and recombined attB/P sites template respectively. The result implies good orthogonalilty between most integrases in that only the band of corresponding recombined attB/P site appears after induction. However, we find that integrase phiRv1 can invert the sequence between attB and attP sites of integrase phiC31. By the way, the leakage of integrase Bxb1 and TG1 is obvious. We have discuss this leakage in diffusion model part.
The efficiency of the integrases
If we want to build meaningful sequential memory modules, integrases we use in our system should have high efficiency, which means low leakage and high percentage of recombinant after induced. So, we designed experiment to investigate original sites versus recombinants.
Another type of testing plasmids was constructed(Fig.6). Sites of phiBT1, Bxb1, phiC31, phiRv1 and TG1 were tested using qPCR, quantitively measuring the percentage of recombinants.
All of the integrase are able to catalyze the recombination reaction in our system. Among 5 integrases, phiBT1 shows the best feature of staying low and steady recombined attL/R rate before induction and reaching high rate after induced. phiBT1 is good enough for building sequential memory structures and being a basic memory device. Although phiC31 achieves low-rate recombination, but the induction can make an obvious difference. As a result, it is enough for us to use phiC31 as a memory device. Other integrases are difficult to control by inducing due to high leakage or other reasons. However, some integrases such as Bxb1 show good performance in other teams' system, so we think the result may be affected by the system we designed(two plasmid system) in this experiment.
Validation of the sequential memory structures
The key part of our project is the sequential memory structures, making validating this part the most important work. Unluckily, we are still working on this. In Fig.8, we show the plasmid we are working on.
Oops! We are now constructing the plasmid, and still working on this.